Uniform Instruction Length (RISC) vs. Variable Instruction Length (CISC) Kris Stewart, CS 575, Fall 03 (upd) ---------------------------------------------------------------------- Expands on material from text, HPC by Dowd & Severance , p. 18-19 Fig. 2-5 CISC: Instruction 1: R1 <- [addr(A)] + 4 *R2 + 1 Instruction 2: return The CISC hardware would need, for example, 20 bits for the addr(A), 20 bits for the constant 4, 20 bits for the constant 1, someway to code the input register R2 and someway to code the output register R1 Or the CISC designer would limit the range of "constants" to reduce the number of bits needed from 20. Lots of ways to go here. We will not try to optimize the usage of registers, instead used the same incremental steps as our text's Fig. 2-5 RISC: Instruction 1: R3 <- 4*R2 Instruction 2: R4 <- addr(A) + R3 *** NOTE: typo in text p. 19 *** Instruction 3: R5 <- [R4] Instruction 4: R1 <- R5 + 1 Instruction 5: return The hardware designer might establish a convention for how the instructions are specified. So let's assume our Load/Store architecture expects the following to be specified for the instructions above: Target Input Reg OP Reg Addr or constant ------ ----- ----- ----------- 3 * 2 immediate 4 (constant 4) 3 + 3 A's address 5 memref 3 contents of input register (R3 constructed) 1 + 5 immediate 1 (constant 1) 4 bits +4 bits +4 bits +20 bits => 32 bit word to hold instruction 4 bits could specify 16 different registers 0,...,15 4 bits could specify 16 different operations * + memref and or ... 20 bits could specify an address in 1 MB memory or an integer constant whose value is the the range +/- 500K 2^20 = 1048576, therefore in 20 bits we can directly specify the address of word 0 through word 1048575 for a simple linearly ordering of memory. Actual HPC architectures use more elaborate memory bank organizations which we will discuss next week in Chapter 3. 20 bits can also represent integer numbers and we'd want both positive and negative values so that's why I have the "range +/- 500K" above.